Elansat-tech OTP ROM EM78P156N User Manual

EM78P156N OTP ROM EM78P156N 8-BIT MICRO-CONTROLLER Version 1.2 WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.TW WWW.100Y.COM.

EM78P156N OTP ROM Address R PAGE registers IOC PAGE registers 00 R0 (IAR) Reserve 01 R1 (TCC) CONT(Control Register) 02 R2 (PC) Reserve 03 R3 (Sta

EM78P156N OTP ROM 4. R3 (Status Register) 7 6 5 4 3 2 1 0 GP2 GP1 GP0 T P Z DC C • Bit 0 (C) Carry flag • Bit 1 (DC) Auxiliary carry fla

EM78P156N OTP ROM • RF can be cleared by instruction but cannot be set. • IOCF is the interrupt mask register. • Note that the result of reading RF

EM78P156N OTP ROM • CONT register is both readable and writable. 3. IOC5 ~ IOC6 (I/O Port Control Register) • "1" put the relative I/O pin

EM78P156N OTP ROM • Bit 5 (OD5) Control bit is used to enable the open-drain of P65 pin. • Bit 6 (OD6) Control bit is used to enable the open-drain

EM78P156N OTP ROM Setting the ROC to "1" will enable the status of R-option pins (P50∼P51) that are read by the controller. Clearing the R

EM78P156N OTP ROM CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from external clock input, TCC is increased by 1 at eve

EM78P156N OTP ROM R-option function is used, it is recommended that P50~P51 are used as output pins. When R-option is in enable state, P50~P51 must

EM78P156N OTP ROM PCRDPCWRPDWRPDRDTINIODP61~P67PORT01MUXCLKCLKCLKPPPLLLRRRCCCDDDQQQQQQ___ NOTE: Pull-high (down) and Open-drain are not shown in t

EM78P156N OTP ROM Table 4 Usage of Port 6 Input Change Wake-up/Interrupt Function Usage of Port 6 input status changed Wake-up/Interrupt (I) Wake-up

EM78P156N OTP ROM Specification Revision History Version Content 1.0 Initial version 1.1 Change Power on reset content 07/01/2003 1.2 Add t

EM78P156N OTP ROM 4.5 RESET and Wake-up 1. RESET A RESET is initiated by one of the following events- (1) Power on reset. (2) /RESET pin input "

EM78P156N OTP ROM vector following wake-up. If ENI is executed before SLEP, the instruction will begin to execute from the address 008H after wake-u

EM78P156N OTP ROM Table 5 The Summary of the Initialized Values for Registers Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit

EM78P156N OTP ROM Address Name Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0/RESET and WDT P P P P P P P P Wake-Up from Pin Chang

EM78P156N OTP ROM 1. A power-on condition, 2. A high-low-high pulse on /RESET pin, and 3. Watchdog timer time-out. The values of T and P, listed in

EM78P156N OTP ROM 4.6 Interrupt The EM78P156N has three falling-edge interrupts listed below: (1) TCC overflow interrupt (2) Port 6 Input Status Cha

EM78P156N OTP ROM INTENI/DISIIODRFWRIOCFRDIOCFWRIRQnIRQmRFRDIOCF/RESET/IRQnVCCRFCLKCLKQQDPRLC_PRLCQQ_D Fig. 10 Interrupt Input Circuit 4.7 Oscillato

EM78P156N OTP ROM Table 9 The Summary of Maximum Operating Speeds Conditions VDD Fxt max.(MHz)3.0 8.0 Two cycles with two clocks 5.0 20.0 2. Cryst

EM78P156N OTP ROM Table 10 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator Oscillator Type Frequency Mode Frequency C1(pF)

EM78P156N OTP ROM OSCI EM78P156NVccRextCext Fig. 13 Circuit for External RC Oscillator Mode Table 11 RC Oscillator Frequencies Cext Rext Avera

EM78P156N OTP ROM 1. GENERAL DESCRIPTION EM78P156N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS technology.. It

EM78P156N OTP ROM Word 0 Word 1 Bit12~Bit0 Bit12~Bit0 1. Code Option Register (Word 0) WORD 0 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4

EM78P156N OTP ROM 0 1 1 Enable 1 0 0 Enable 1 0 1 Enable 1 1 0 Enable 1 1 1 Disable 2. Customer ID Register (Word 1) Bit 12~Bit 0 XXXXXXXX

EM78P156N OTP ROM EM78P156N /RESET Vdd DRRinC Fig. 14 External Power-Up Reset Circuit 4.11 Residue-Voltage Protection When battery is replaced, dev

EM78P156N OTP ROM EM78P156N /RESETVddQ1Vdd 40KR2R1 Fig. 16 Circuit 2 for the Residue Voltage Protection 4.12 Instruction Set Each instruction in th

EM78P156N OTP ROM (2) The I/O register can be regarded as general register. That is, the same instruction can operate on I/O register. The symbol &q

EM78P156N OTP ROM R(7) → C, C → A(0) 0 0110 11rr rrrr 06rr RLC R R(n) → R(n+1), R(7) → C, C → R(0) C 0 0111 00rr rrrr 07rr SWAPA R R(0-3

EM78P156N OTP ROM 4.13 Timing Diagrams RESET Timing (CLK="0")CLK/RESETNOPInstruction 1ExecutedTdrhTCC Input Timing (CLKS="0")CLK

EM78P156N OTP ROM 5. ABSOLUTE MAXIMUNM RATINGS EM78P156N Items Rating Temperature under bias -40°C to 85°C Storage temperature -65°C to 150°C Worki

EM78P156N OTP ROM 6. ELECTRICAL CHARACTERISTICS 6.1 DC Electrical Characteristic (Ta=25 °C, VDD=5V±5%, VSS=0V) Symbol Parameter Condition Min Ty

EM78P156N OTP ROM 6.2 AC Electrical Characteristic (Ta=25 °C, VDD=5V±5%, VSS=0V) Symbol Parameter Conditions Min Typ Max Unit Dclk Input CLK

EM78P156N OTP ROM 2. FEATURES • Operating voltage range : 2.5V~5.5V • Operating temperature range: -40°C~85°C • Operating frequency rang (base on

EM78P156N OTP ROM 6.3 Device Characteristic The graphs provided in the following pages were derived based on a limited number of samples and are sh

EM78P156N OTP ROM Vth (Input thershold voltage) of I/O pins00.511.522.5 3 3.5 4 4.5 5 5.5VDD (Volt)Vth (Volt) Max(-40℃ to 85℃) Typ 25℃Min(-40℃ to 85

EM78P156N OTP ROM Voh/Ioh (5V)-25-20-15-10-501.522.533.544.55Voh (Volt)Ioh (mA) Voh/Ioh (3V)-10-8-6-4-2000.511.522.53Voh (Volt)Ioh (mA) Min 85℃Min

EM78P156N OTP ROM Vol/Iol (3V)05101520253035404500.511.522.53Vol (Volt)Iol (mA) Vol/Iol (5V)01020304050607080901000 0.5 1 1.5 2 2.5 3Vol (Volt)Iol (

EM78P156N OTP ROM WDT Time out05101520253035404523456VDD (Volt)WDT period (mS) Max 85℃ Max 70℃Typ 25℃Min 0℃Min -40℃ Fig. 23 WDT time out period vs

EM78P156N OTP ROM Cext = 100pF, Typical RC Frequency vs. VDD00.20.40.60.811.21.41.63 3.5 4 4.5 5 5.5VDD (Volt)Frequency (M Hz) R = 3.3KR = 5.1KR = 1

EM78P156N OTP ROM Four conditions exist with the Operating Current ICC1 to ICC4. These conditions are as follows: ICC1: VDD=3V, Fosc=32K Hz, 2 cloc

EM78P156N OTP ROM Typical ICC3 and ICC4 vs. Temperature00.511.522.533.54-40 -20 0 20 40 60 80Temperature (℃)Current (mA) Typ ICC4Typ ICC3Fig. 28 Typ

EM78P156N OTP ROM Two conditions exist with the Standby Current ISB1 and ISB2. These conditions are as follows: ISB1: VDD=5V, WDT disable ISB2: VDD

EM78P156N OTP ROM Fig. 32 Operating voltage in temperature range from 0℃ to 70℃ Fig. 33 Operating voltage in temperatu

EM78P156N OTP ROM * 20 pin SSOP 209mil : EM78P156NKM • 99.9% single instruction cycle commands • The transient point of system frequency between

EM78P156N OTP ROM EM78P156N-J HXT V-I00.250.50.7511.251.51.7522.252.52.3 2.8 3.3 3.8 4.3 4.8 5.3Voltage(V)I(mA) Fig. 34 Operating current range (ba

EM78P156N OTP ROM EM78P156N-G HXT V-I00.250.50.7511.251.51.7522.252.52.3 2.8 3.3 3.8 4.3 4.8 5.3Voltage(V)I(mA) Fig. 36 Operating current range (ba

EM78P156N OTP ROM APPENDIX Package Types: OTP MCU Package Type Pin Count Package Size EM78P156NP DIP 18 300 mil EM78P156NM SOP 18 300 mil EM

EM78P156N OTP ROM Package Information 18-Lead Plastic Dual in line (PDIP) — 300 mil This specification is subject to change without prior

EM78P156N OTP ROM 18-Lead Plastic Small Outline (SOP) — 300 mil This specification is subject to change without prior notice. 54

EM78P156N OTP ROM 20-Lead Plastic Small Outline (SSOP) — 209 mil This specification is subject to change without prior notice. 55 0

EM78P156N OTP ROM Quality Assurance And Reliability Test category Test conditions Remarks Solderability Solder temperature=245±5℃，for 5 seconds up

EM78P156N OTP ROM /ReseInternal PORPower onTporTvdTvr Vdd Symbol Parameter Condition Min. Typ. Max. Unit Tpor Power on reset time V

EM78P156N OTP ROM 3. PIN ASSIGNMENTS TCCVDDVssP50P51P53P60/INTP61P62P63 P64P52/RESETOSCIOSCOP67P66P65EM78P156NPEM78P156NM123456789161514131211101718

EM78P156N OTP ROM Table 2 EM78P156NAS Pin Description Symbol Pin No. Type Function VDD 15 - * Power supply. OSCI 17 I * XTAL type: Crystal i

EM78P156N OTP ROM 4. FUNCTION DESCRIPTION InterruptControllerROMInstructionRegisterInstructionDecoderR2ALUStackACCR3R4Oscillator/TimingControlWDT ti

EM78P156N OTP ROM 3. R2 (Program Counter) & Stack • Depending on the device type, R2 and hardware stack are 10-bits wide. The structure is depic